1) Field of the Invention
The present invention relates to a method and a device for obtaining a sum of products using integrated circuits (IC's) and utilized in a picture (or image) processing system using a spatial filtering method, and in particular, to a method and a device for obtaining a sum of products using a predetermined number of multipliers and adders for summing the products.
2) Description of the Related Art
A device for obtaining a sum of products is used in a picture processing system or in radio communication equipment. In the former, each pixel of a picture is processed by the device. A result, a smoother, enhanced, or contour-emphatic picture is obtained. The device is applied in the processing of a picture from a weather satellite, a parts inspection apparatus in a factory, a viewing robot, or the like. In the latter, the device is used as an element in a transversal equalizer, to increase the quality of the transmission signal.
A sum of products is obtained by calculating the products of pairs of multiplicands and multipliers, and then adding the total products. When this calculation is performed by IC's, usually the number of devices used is in accordance with the scale of the operation. Namely, first a desired number of multipliers (number of pairs of the object to be multiplied) is provided. The products of these pairs are calculated by the multiplier and a plurality of products is obtained. The products are added two by two and a corresponding sum is obtained for each addition. Each sum is then further added two by two, and this calculation operation is repeated until the total sum of products is obtained.
When the above operation is performed, the only problem with the multipliers is the capacity of an IC to cope with the number of multipliers and the figure length of the operand applied to the multiplier. The "figure length", i.e., number of numeric characters, handled by this multiplier is determined by the figure length of the multiplicand and multiplier. On the other hand, for the adders, the sums to be calculated increase as the processing advances. This requires a change of the scale of the adder in response to the stage at which the adder is located. That is, an IC having the same rating cannot be used for all of the adders. The present invention has been created to solve this problem, and satisfies the above operation needs by using a plurality of IC's having the same rating.